The present invention relates to a pseudo-static semiconductor memory device, and more particularly to an internal refresh circuit of the memory device with a variable cycle of self-refresh operation.
A semiconductor dynamic memory device has a very large memory capacity with a low cost because of a very simple memory cell structure. It uses the so-called "one transistor memory cell" which consists of one insulated gate field effect transistor (IGFET) such as an MOS (Metal-Oxide-Semiconductor) transistor and one storage capacitor. Since the charges stored in the memory cell capacitor decrease by leakage, they should be restored periodically through a refresh operation. The refresh operation in the dynamic memory device is carried out by supplying external address signals in synchronism with external clock signals, but a control circuit of the external clock is complicated.
To avoid the complicated external circuit, a memory device provided with an internal refresh circuit has been proposed. Such a memory device is called as a "pseudo-static memory device". The internal refresh circuit includes a refresh control circuit, an internal address counter and a timer circuit. The refresh control circuit is activated by a refresh signal applied externally to a refresh terminal of the memory device, to supply the content of the internal address counter to a row decoder as a row address signal. The row decoder selects one of the rows of a memory cell array to refresh the memory cells on the selected row. Thereafter, the internal address counter is incremented or decremented by one. On the other hand, the refresh control circuit enables the timer circuit, which thereby generates a refresh request signal in a predetermined time period. In response to the refresh request signal, the incremented or decremented content of the internal address counter is supplied to the row decoder to select the next row and the memory cells on the next row are refreshed. The content of the internal address counter is then further incremented or decremented by one and supplied to the row decoder in response to a next refresh request signal generated in a predetermined cycle. Thus, the self-refresh operation continues at each time when the timer circuit generates the refresh request signal, so long as the refresh signal is applied, with a cycle equal to the cycle of generation of the refresh request signal.
If the refreshing interval is too long, the leakage of the storage capacitor makes it impossible to determine whether the stored information is "1" or "0". The critical time interval is called a "data-hold time". Accordingly, the cycle of the self-refresh operation, i.e., the generation cycle of the refresh request signal in the timer circuit, should be selected such that all the memory cells are refreshed at least once within the data-hold time.
As an ambient temperature increases, the leakage of the storage capacitor becomes large and the data-hold time becomes short. Therefore, the generation cycle of the refresh request signal should be as short as possible in order that all the memory cells be refreshed within the data-hold time even in a highest ambient temperature. This means that the refresh operation is unnecessarily done many times in room temperature or in a lower temperature. Since a power consumption in the refresh operation depends upon times of refresh operation, it rises as the cycle of the self-refresh operation becomes short and the unnecessary refresh operation brings about an unnecessary power consumption. The self-refresh operation is generally carried out in the standby condition of the memory device, wherein a back-up power source such as a battery is used as a power source of the memory device. Accordingly, power consumption is unnecessarily large in the standby condition.